1. Field of the Invention
This invention relates to MOSFET semiconductor devices and more particularly to flash memory cells.
2. Description of Related Art
A flash memory cell using split gate structure, which can overcome the problem of over-erasing, was demonstrated by Seeq, Solid State Ckt, pp 676-683 (1987). However, it is known that the split gate structure, as demonstrated in the above paper has the drawback of an endurance problem, since the programming and the erasing operations are through the same drain region junction.
As shown in a publication IEEE Electron-Devices letter, pages 117-119 (March 1989) when erasing by Fowler-Nordheim (F-N) tunneling and programming by channel-not-electron are through the same drain region junction, the cell's programmability degradation is much worse than the erasing being separated to source junction such as U.S. Pat. No. 4,780,424, No. 4,678,787, and No. 5,106,772.
However in a split-gate structure, the source junction is not directly underneath the floating gate as it is in a conventional stacked cell structure. Therefore, no Fowler-Nordheim (F-N) tunneling through the source is feasible as illustrated by FIG. 1.
U.S. Pat. No. 5,070,032, No. 4,853,895 and No. 4,998,220 used a third layer of polysilicon over the polysilicon 1 (Floating area) as the erase gate to perform so-called polysilicon to polysilicon erasing which can avoid the operation of programming/erasing being through the same drain region junction. However, third polysilicon erasing cell structure increases cell size and the process complexity significantly. Also oxide grown over polysilicon as tunneling material suffers more of a reliability problem.
An object of this invention is to provide programming of a flash memory cell.